The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device using a resonant-tunneling transistor (hereinafter simply referred to as an RTT).
Generally, in a static random access memory (SRAM), at least four field effect transistors (FETs) are used to constitute one memory cell. Out of the four FETs, two FETs are used for flip-flop circuit and the remaining two FETs are used for a transfer gate. On the other hand, in the case of double emitter bipolar transistors, at least two double emitter bipolar transistors are used to constitute one memory cell.
Presently, one of the greatest technical problems to be solved in semiconductor integrated circuit devices concerns the realization of a high integration density, and a semiconductor memory device is no exception.
Conventionally, in order to obtain a high integration density, attempts have been made to miniaturize the transistor itself. But sooner or later, it will reach a stage of deadlock where the miniaturization of the transistor is carried out to the limit according to the present technology. For this reason, it is necessary to take other measures to obtain the high integration density.
One conceivable method of breaking the deadlock in the realization of the high integration density is to reduce the number of transistors constituting the semiconductor integrated circuit device without changing the function and effect of the semiconductor integrated circuit device. However, in the case of the semiconductor memory device, it is reaching a stage of deadlock where the demands have been satisfied to a point near the limit according to the present technology, as long as ordinary transistors are used.
Therefore, there is a strong demand to realize a semiconductor memory device the integration density of which can be increased considerably.